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| TEA6425 VIDEO CELLULAR MATRIX s s s s s s s s s 6 Video Inputs - 8 Video Outputs 2 Internal Selectable YC Adders 15MHz Bandwidth @ -3dB Selectable 0.5/6.5dB Gain FOR EACH Output High Impedance Switch for each Output (3state operation) Programmable Clamp Mode on each Input (sync bottom or average value) -60dB Crosstalk @ 5MHz 4 Sub-address Capability I2C Bus Control DIP20 (Plastic Package) ORDER CODE: TEA6425 DESCRIPTION This device is intended for switching between video and chroma signals such as CVBS, SVHS, baseband CVBS, MAC. Each input clamp mode, each output gain, all switching are controlled through the I2C bus. The 8 outputs can be set separately in high impedance state, to enable parallel DC connection of several devices (up to 4). SO20L (Plastic Micropackage) ORDER CODE: TEA6425D Figure 1. Pin Connections IN 1 SDA 1 20 V CC OUT 1 2 3 4 5 6 19 18 17 16 15 IN 2 SCL IN 3 IN 4 SUB OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 7 8 9 10 14 13 12 11 IN 5 V CCP IN 6 OUT 7 OUT 8 GND September 2003 1/10 6425-01.eps 1 TEA6425 Figure 2. Block Diagram 1 PROG. CLAMP PROG. CLAMP PROG. CLAMP PROG. CLAMP PROG. CLAMP PROG. CLAMP 3 INPUTS 5 6 6x8 MATRIX 8 10 SCL SDA SUB-ADDRESS 4 2 7 0/6 dB 0/6 dB 0/6 dB 0/6 dB 0/6 dB 0/6 dB 0/6 dB 0/6 dB I2C DECODER VCC1 9 3 STATE OUTPUTS TEA6425 11 GND 12 13 14 15 16 17 18 19 OUTPUTS Figure 3. Cellular Matrix Connections 1st/4 addresses 2nd/4 addresses CVBS or C I2 C DECODER I2 C DECODER PROG. CLAMP 6 INPUTS ADDER 0dB 6dB 3 STATE OUT IC4 8 OUTPUTS LINES 2/10 1 6425-03.eps IC3 6 INPUTS 6X8 Full MATRIX IC1 6X8 Full MATRIX IC2 6425-02.eps VCC2 20 TEA6425 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI Toper Tstg Parameter Supply Voltage Voltage at Pin i to GND Operating Ambient Temperature Storage Temperature Value 12 0, VCC 0, + 70 -20, + 150 Unit V V oC oC THERMAL DATA Symbol Rth (j-a) Parameter Junction-ambient Thermal Resistance Min. Value 80 o Unit C/W ELECTRICAL CHARACTERISTICS (VCC = 8V, Tamb = 25oC, VIN = 1V, Gain = 6.5dB, Cload = 20pF, Rload = 4.7k ; Gain condition, clamp and 3-state are controlled by I 2C bus, unless otherwise specified) Symbol Parameter Test Conditions SUPPLY Supply Voltage VCC Supply Current ICC RR Supply Voltage Rejection f = 1kHz VIDEO INPUTS (clamping at bottom sync level) Max. Signal Amplitude Clamp Active VIN Vclamp Clamp Level Clamp Active Input DC Level Clamp Inactive VDC Leakage Current 1 input connected to 1 output IIN Clamp Current Vclamp - 200mV Iclamp VIDEO OUTPUTS Output Resistance ROUT Output "off" Impedance no load ZHI COUT in 3-state no load CHI G1 Voltage Gain f = 100kHz G2 Voltage Gain f = 100kHz Top Level Sync (Y or CVBS) G = 6.5dB, Clamp Active Vsync G = 0.5dB, Clamp Inactive Output Mean Level (chroma) Vbias G = 6.5dB, Clamp Inactive Isolation "off" State f = 5MHz Crosstalk Attenuation between f = 5MHz Channels B Bandwidth Cload = 20pF, G = 6.5dB at 0.5dB at 1dB at - 3dB Min. 7.2 40 2 1.7 2.7 Typ. 8 45 46 Max. 8.8 60 Unit V mA dB VPP V V A mA W k pF dB dB V V V dB dB 2 3 2 0.9 15 2.3 3.3 5 3 50 50 0 6 1 2 3 60 50 3 0.5 6.5 1.25 2.4 3.4 1 7 2 3 4 60 5 10 21 MHz FUNCTIONAL DESCRIPTION This device is controlled via the I2C bus. 4 addresses can be selected by a 4-level detector on Pin 7, thus enabling parallel connection of 4 devices. Via the I2C bus : - The input signals can be clamped at their negative peak (top sync). - The gain factor of the outputs can be selected between 0.5 and 6.5dB. - Each of the 6 inputs can be connected to the 8 outputs. - Each output can individually be set in a high impedance state. Two internal SVHS mixers will add the selected Y and C inputs. Two dedicated outputs will have the option to select this added signal also. 3/10 1 TEA6425 I2C BUS CHARACTERISTICS Symbol SCL VIL VIH ILI fSCL tR tF CI SDA VIL VIH ILI CI tR tF VOL tF CL TIMING tLOW tHIGH tSU, DAT tHD, DAT tSU, STO tBUF tHD, STA Parameter Test Conditions Standard Mode Min. Max. - 0.3 3.0 - 10 0 + 1.5 VCC + 0.5 + 10 100 1000 300 10 + 1.5 VCC + 0.5 + 10 10 1000 300 0.4 250 400 Fast Mode Min. Max. Unit Low Level Input Voltage High Level Input Voltage Input Leakage Current Clock Frequency Input Rise Time Input Fall Time Input Capacitance Low Level Input Voltage High Level Input Voltage Input Leakage Current Input Capacitance Input Rise Time Input Fall Time Low Level Output Voltage Output Fall Time Load Capacitance VI = 0 to VDD 1.5V to 3V 1.5V to 3V - 0.3 + 1.5 V 3.0 VCC + 0.5 V - 10 + 10 A 0 400 kHz 300 ns 300 ns 10 pF - 0.3 + 1.5 3.0 VCC + 0.5 - 10 + 10 10 300 300 0.4 250 400 1.3 0.6 100 0 0.6 1.3 0.6 0.6 V V A pF ns ns V ns pF s s ns ns s s s s VI = 0 to VDD 1.5V to 3V 1.5V to 3V IOL = 3mA 3V to 1.5V - 0.3 3.0 - 10 Clock Low Period Clock High Period Data Set-up Time Data Hold Time Set-up Time from Clock High to Stop Start Set-up Time following a Stop Start Hold Time Start Set-up Time following Clock Low-to tSU, STA High Transition 4.7 4.0 250 0 4.0 4.7 4.0 4.7 340 340 Figure 4. I2C Bus Timing SDA t BUF t LOW tf SCL t HD,STA tr t HD,DAT t HIGH t SU,DAT t SU,STA t SU,STO 4/10 1 6425-04.eps SDA TEA6425 I2C BUS SELECTION I2C Bus Slave Address Address Value A6 1 A5 0 A4 0 A3 1 A2 0 A1 A1 A0 A0 R/W 0 I2C Sub-Address Symbol Vsub 1 2 3 4 Parameter Slave address HEXA 90 96 94 92 Conditions Sub-address (see note) A0 A1 0 0 1 1 0 1 1 0 Pin 7 Voltage (Typ) Unit GND VCC 1/3 2/3 V V VCC VCC Note: The first 3 levels are defined by connecting the sub-address pin to the appropriate level. Sub-address 4 will be selected when this pin is left open. 1st Data Byte b7 a2 0 0 0 0 1 1 1 1 b6 a1 0 0 1 1 0 0 1 1 b5 a0 0 1 0 1 0 1 0 1 b4 * * * * * * * * * b3 * * * * * * * * * b2 * * * * * * * * * b1 * * * * * * * * * b0 I 0 0 0 0 0 0 0 0 Selected Output OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 Output Select 2nd Data Byte b7 a2 0 0 0 0 1 1 * * * * * * * * b6 a1 0 0 1 1 0 0 * * * * * * * * b5 a0 0 1 0 1 0 1 * * * * * * * * b4 * * * * * * * 0 1 * * * * * * b3 * * * * * * * * * 0 1 * * * * b2 * * * * * * * * * * * 0 1 * * b1 * * * * * * * * * * * * * 0 1 b0 I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Selected Output IN1 IN2 IN3 IN4 IN5 IN6 Free Clamped 0.5dB 6.5dB Disabled Enabled Low impedance Tri-state Input Select Clamp Gain Mixer Tri-state Power-on-Reset When active: outputs in 3-state, inputs are clamped Symbol Reset End of Reset Parameter Start of Reset Test Conditions Incr. VCC Decr. VCC Incr. VCC Min. Typ. Max. 2.5 4.2 Unit V V V 4.5 5/10 1 TEA6425 PIN CONFIGURATIONS Figure 5. Video IN Clamp V REF V REF Clamp Pins 1 - 3 - 5 6 - 8 - 10 to Matrix Figure 6. Video OUT TRI-STATE TRI-STATE TRI-STATE Pins 12 - 13 - 14 - 15 16 - 17 - 18 - 19 From Matrix TRISTATE TRI-STATE V REF 6425-06.eps TRISTATE TRISTATE TRISTATE Figure 7. PROG Pin Figure 8. Bus Inputs VC C VC C 20k ESD PROT. 7 40k VREF to CMOS Pins 2-4 V REF to CMOS X4 ACKN 6425-07.eps 6425-08.eps 3 TIMES IN // For SDA only 6/10 1 6425-05.eps TEA6425 Figure 9. Typical Application V CC (+8V) 22F 10H 75 Y 220nF 220nF C 75 EXT SVHS OUT 4.7k 9 C1 Y1 SVHS1 IN 4.7k 11 20 19 1 C2 3 2x 75 C3 5 C1 C4 C5 Y2 SVHS2 IN 6 8 C6 C2 2x 75 I2 C 10 2 SDA SCL 2 T E A 6 4 2 5 4 7 TO PIP PROCESSOR (CVBS or Y+C) 4.7k 18 17 16 15 14 13 12 CVBS/Y C TO TV PROCESSOR (CVBS or YC) 4 7 75 19 SCART 1 (CVBS OUT) SCART 2 (CVBS OUT) SCART 3 (CVBS OUT) TUNER OUT (CVBS) SCART 1 (CVBS IN) C7 C8 1 3 C9 SCART 2 (CVBS IN) C10 SCART 3 (CVBS IN) 3x 75 C11 5 6 8 C12 10 9 220nF T E A 6 4 2 5 11 20 18 17 16 15 14 75 75 13 12 6x 4.7k Y COMB FILTER C 220nF (CVBS) SVHS 1/2 (Y+C) 6425-09.eps 4.7k 7/10 TEA6425 PACKAGE MECHANICAL DATA 20 PINS - PLASTIC DIP Figure 10. 20-Pin Package 8/10 TEA6425 PACKAGE MECHANICAL DATA (Cont'd) 20 PINS - PLASTIC MICROPACKAGE Figure 11. 20-Pin Package 9/10 TEA6425 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2003 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 10/10 |
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